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| | simd () noexcept=default |
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| | simd (const simd &) noexcept=default |
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| simd & | operator= (const simd &) noexcept=default |
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| JPL_INLINE | simd (Type value) noexcept |
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| JPL_INLINE | simd (float value) noexcept |
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| JPL_INLINE | simd (float v0, float v1, float v2, float v3) noexcept |
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| JPL_INLINE | simd (const float *mem) |
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| JPL_INLINE void | load (const float *mem) |
| | Load values from memory into simd, 'mem' should point to memory with at least size() number of floats.
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| JPL_INLINE void | store (float *mem) const |
| | Store values from simd to provided memory location.
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| JPL_INLINE float | operator[] (uint32 index) const noexcept |
| | Get float component by index.
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template<uint32 LaneIndex>
requires (LaneIndex < 4) |
| JPL_INLINE float | get_lane () const noexcept |
| | Get float component by index known at compile-time.
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| JPL_INLINE simd | operator* (const simd &other) const noexcept |
| | Multiply two float vectors (component wise)
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| JPL_INLINE simd | operator* (float value) const noexcept |
| | Multiply vector with float.
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| JPL_INLINE simd | operator/ (float value) const noexcept |
| | Divide vector by float.
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| JPL_INLINE simd & | operator*= (float value) noexcept |
| | Multiply vector with float.
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| JPL_INLINE simd & | operator*= (const simd &other) noexcept |
| | Multiply vector with vector.
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| JPL_INLINE simd & | operator/= (float value) noexcept |
| | Divide vector by float.
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| JPL_INLINE simd & | operator/= (const simd &other) noexcept |
| | Divide vector by vector.
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| JPL_INLINE simd | operator+ (const simd &other) const noexcept |
| | Add two float vectors (component wise)
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| JPL_INLINE simd & | operator+= (const simd &other) noexcept |
| | Add two float vectors (component wise)
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| JPL_INLINE simd | operator- () const noexcept |
| | Negate.
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| JPL_INLINE simd | operator- (const simd &other) const noexcept |
| | Subtract two float vectors (component wise)
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| JPL_INLINE simd & | operator-= (const simd &other) noexcept |
| | Subtract two float vectors (component wise)
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| JPL_INLINE simd | operator/ (const simd &other) const noexcept |
| | Divide (component wise)
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| JPL_INLINE void | operator|= (const simd &other) noexcept |
| | Component-wise logical OR.
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| JPL_INLINE void | operator^= (const simd &other) noexcept |
| | Component-wise logical XOR.
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| JPL_INLINE void | operator&= (const simd &other) noexcept |
| | Component-wise logical AND.
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template<uint32 LaneIndex>
requires (LaneIndex < 4) |
| JPL_INLINE simd | splat () const |
| | Replicate component at LaneIndex to all components.
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| JPL_INLINE float | reduce () const noexcept |
| | Returns sum of all components.
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| JPL_INLINE float | reduce_max () const noexcept |
| | Returns max component.
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| JPL_INLINE float | reduce_min () const noexcept |
| | Returns min component.
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| JPL_INLINE float | reduce_mean () const noexcept |
| | Returns mean of the components.
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| JPL_INLINE | operator Type () const noexcept |
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| JPL_INLINE simd_mask | to_mask () const noexcept |
| | Convert each component from a float to an int.
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| JPL_INLINE simd_mask | as_mask () const noexcept |
| | Reinterpret simd as a simd_mask (doesn't change the bits)
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| template<int Scale> |
| static JPL_INLINE simd | gather (const float *base, const simd_mask &offsets) |
| | Gather 4 floats from memory at base + offsets[i] * Scale.
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| static JPL_INLINE simd | zero () noexcept |
| | Vector with all zeros.
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| static JPL_INLINE simd | nan () noexcept |
| | Vector with all NaN's.
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| static JPL_INLINE simd | inf () noexcept |
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| static JPL_INLINE simd | c_0 () noexcept |
| | Frequently used constants.
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| static JPL_INLINE simd | c_1 () noexcept |
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| static JPL_INLINE simd | c_0p5 () noexcept |
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| static JPL_INLINE simd | c_pi () noexcept |
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| static constexpr std::size_t | size () noexcept |
| | Get number of element of the vector.
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| static JPL_INLINE simd | select (const simd_mask &mask, const simd &a, const simd &b) noexcept |
| | Component-wise select, returns 'a' if mask is true, 'b' otherwise.
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| static JPL_INLINE simd | reciprocal (const simd &vec) noexcept |
| | Reciprocal vector (1 / value) for each of the components.
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Minimal 4-wide 32-bit float vector implementation for SIMD.